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124 IP
51
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
52
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
53
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
54
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
55
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
56
0.3729
PCI/PCIX Interface 1.8V Oxide Device- TSMC 22nm 22ULP,ULL
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
57
0.3729
PCI/PCIX Interface 1.8V Oxide Device - TSMC 28nm 28HP, 28LP, 28ULP, 28HPL, 28HPC, 28HPC+, 28HPM
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
58
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process....
59
0.118
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process....
60
0.118
PCIe Gen4 x8 Lane Endpoint Controller
PCIe Gen4 x8 Lane Endpoint Controller...
61
0.118
The PCIe Gen3 PCS for 28nm programmable serdes.
The PCIe Gen3 PCS for 28nm programmable serdes....
62
0.0
12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...
63
0.0
16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base Specification with su...
64
0.0
PCI Express (PCIe) 6.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...
65
0.0
PCI Express (PCIe) 7.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...
66
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
The PCIe 2.0 transceiver IP supports all PCIe 2.0 Base applications. It complies with the PIPE 3.0 standard. This IP incorporates high-speed mixed sig...
67
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fund...
68
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
PCIe Gen 2 PHY IP is a physical layer (PHY) IP solution for consumer electronics, that allows for a full featured customization and complies with the ...
69
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customizati...
70
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. In order to enable PCIe ...
71
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. The PCIe 2.0 data rate at...
72
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits t...
73
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP integrates mixed signal cir...
74
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 40ULP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mi...
75
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base speci...
76
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to f...
77
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mi...
78
0.0
PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...
79
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification. The Gen 3 has a capability for extr...
80
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 14SFP
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...
81
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 28SF
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lo...
82
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard. Because the low power mode op...
83
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design. The PCIe 3.0 IP complies with the P...
84
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
High-bandwidth applications can avail advantage of PCIe 3.0 PHY IP's high performance, multi-lane scalability, and low-power layout. A full variety of...
85
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design. It fully supports a wide ra...
86
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Low pow...
87
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the sup...
88
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the sup...
89
0.0
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with PCIe 3.0 Base Specific...
90
0.0
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
(PCIe 3.1) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input...
91
0.0
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP. With compatibility for PIPE 4.3 interface spec, this complies with PCIe Rev3 Base Spec...
92
0.0
PCIe 3.1/2.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm, 40nm and 55nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 3.1 IP suppo...
93
0.0
PCIe 4.0 PHY IP for SS 14LPU
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
94
0.0
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design. A full variety of PCIe...
95
0.0
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PCIe 4.0 Base Specifica...
96
0.0
PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 Base Specification. C...
97
0.0
PCIe 4/3/2 SerDes PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
98
0.0
PCIe 5.0 IP on Samsung SF5
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...
99
0.0
PCIe 5.0 PHY for SF5
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
100
0.0
PCIe 5.0 PHY IP for TSMC N5
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s application...